Field of the Invention
The present invention relates to an integrated memory that can be subjected to a memory cell test in order to ascertain operable and faulty memory cells and has addressable memory cells that are configured in a matrix-like memory cell array along column lines and row lines and are combined to form groups of column lines and row lines. The invention also relates to a method for checking the operation of memory cells in such a memory.
To check the operability of memory cells in an integrated memory, the integrated memory is generally subjected to a memory cell test. During such a test mode for checking memory cells, test data are written to each individual memory cell and are read out again, for example. A comparison between the written data and the data that is read out again indicates whether there is an operating fault in a tested memory cell.
Usually, integrated memories have memory cells configured in a matrix-like memory cell array along column lines and row lines. In this case, the memory cells are combined to form groups of column lines and row lines, for example. In the case of normal redundancy concepts for repairing semiconductor memories, a group of column lines or row lines of the memory cell array is always replaced when there is a fault in a memory cell or in a memory word, which includes a group of memory cells. In terms of a row or column repair to be chosen, the memory cells or memory words situated in the region of intersection of a group of row lines and a group of column lines are equivalent. This means that these memory cells can be repaired by a group of redundant column lines or by a group of redundant row lines.
A repair is initiated if one or more arbitrary memory cells or memory words in the region of intersection fail. To derive the repair information, by way of example, the addresses of the faulty memory cells or the addresses of faulty memory words, also called fault addresses, are stored and processed further for evaluation purposes.
An external test device or a self test unit tests the memory chip by alternately writing and reading data to/from the memory cells of the chip in a particular address sequence and comparing the data with expected data. In this context, an address generator has the task of generating the respective addresses for the write or read operations. The fault information obtained with each accompanying comparison operation can easily be accumulated. By way of example, as soon as a fault has arisen, a xe2x80x9cfault flagxe2x80x9d is set that marks the chip as faulty. If the chip is to be repaired, however, the information about which memory cell is faulty needs to be forwarded to a redundancy analysis unit on or outside the chip. These fault data are used to derive the repair information. To keep down the associated necessary transmission time or channel capacity or signal width for the signal which is to be transmitted, it is expedient for the fault data, for example in the form of fault addresses, to be compressed beforehand, taking account of the redundancy concept of the memory chip.
It is accordingly an object of the invention to provide an integrated memory and a method for checking the operation of memory cells in an integrated memory that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, that checks the operation of memory cells in an integrated memory and that permits extensive compaction of addresses of faulty memory cells.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for checking the operation of memory cells in an integrated memory. The method includes providing an integrated memory having addressable memory cells in a matrix-like memory cell array along column lines and row lines. The memory cells combine to form groups of column lines and row lines, each being addressed using column addresses and row addresses. The column addresses and row addresses each include a first address part addressing the respective groups of column lines and row lines. The next step of the method is testing successively the memory cells in an intersection of one of the groups of column lines and one of the groups of row lines for faults, and then testing memory cells of another group of column lines or row lines. The next step of the method is comparing faulty respective first address parts of the memory cells recognized as being faulty. The next step of the method is processing further the address of a faulty memory cell if the respective first address parts of the faulty memory cells matches another first address part of another faulty memory cell, and not processing further the addresses of other faulty memory cells.
In accordance with a further feature of the invention, the invention of the instant application specifies an integrated memory of the type mentioned in the introduction that permits extensive compaction of addresses of faulty memory cells when carrying out a method for checking the operation of memory cells.
With the objects of the invention in view, there is also provided an integrated memory that can be subjected to a memory cell test in order to ascertain operable and faulty memory cells. The integrated memory includes addressable memory cells in a matrix-like memory cell array. The addressable memory cells are disposed along column lines and row lines. The memory cells combine to form groups of column lines and row lines, each of which are addressed using respective column addresses and row addresses. The column addresses and the row addresses each include a first address part addressing a respective group of the column lines and the row lines, and a second address part addressing memory cells within the respective group. A respective counter generates the first address part and a respective further counter generates the second address part. Each of the counters has control inputs connected to outputs of an addressing unit. The respective first address parts and second address parts of the memory cells to be tested can be tapped off at the output of a respective counter. The addressing unit drives the counters for the purpose of addressing memory cells which are to be tested, such that the memory cells in an intersection of one of the groups of column lines and of one of the groups of row lines are successively addressed. Then, memory cells having another group of column lines or row lines are addressed.
Regarding the method, the object is achieved by a method for checking the operation of memory cells in an integrated memory in which the memory cells each can be addressed using column addresses and row addresses. The column addresses and row addresses of the memory cells each include a first address part addressing the respective groups of column lines and row lines. The method includes the following steps.
Memory cells in the region of intersection of one of the groups of column lines and one of the groups of row lines are successively tested to ensure that there are no faults. Then, memory cells of another group of column lines or row lines are tested.
In the next step, respective first address parts of the memory cells recognized as being faulty are compared.
In the next step, if the respective first address parts of faulty memory cells match, the address of at least one of the faulty memory cells is processed further as the result of the operation check for evaluation purposes. Then, the addresses of other faulty memory cells are not processed further.
In accordance with a further mode of the invention, the memory cells of the integrated memory can each be addressed using column addresses and row addresses. The column addresses and row addresses each include a first address part. The first address part can be used to address the respective groups of column lines and row lines, and a second address part. The second address part can be used to address the memory cells within the respective group having an addressing unit for addressing memory cells which are to be tested, having a respective counter for generating the first address part, and a respective further counter for generating the second address part. Each of which have control inputs connected to outputs of the addressing unit. In these, the respective address parts of the memory cells that are to be tested can be tapped off at the output of the respective counter.
Memory cells or memory words (groups of memory cells) from the same region of intersection are distinguished in that, with the exception of the less significant row and column address bits (second address part), which determine the position within the respective group, they have identical row and column addresses (first address part). In this case, the addresses of faulty memory cells or memory words (fault addresses) can be compressed by comparing successive fault addresses, or first address parts thereof, with one another and no longer forwarding the second and other fault addresses, for example, to a redundancy analysis unit if they belong to the same region of intersection of a group of column lines and a group of row lines as the first fault address which arose.
In this context, a fault address is processed further as the result of the operation check for evaluation purposes. The result can be assessed as xe2x80x9cpass-fail informationxe2x80x9d, for example. It is also possible to establish which of the memory cells are faulty. This can be used as information for subsequent repair of the memory.
For this case, a redundancy concept applied after the operation test stipulates that a group of column lines or a group of row lines is always replaced when there is a fault in a memory cell or in a memory word. A repair is initiated if one or more arbitrary memory cells in the relevant region of intersection are faulty. This means that the information about other faulty memory cells in a region of intersection that is to be tested is not required for subsequent repair because the presence of just one faulty memory cell is sufficient to initiate a repair.
In accordance with a further feature of the invention, the region of intersection of one of the groups of column lines and one of the groups of row lines the, memory cells are successively tested along column lines or row lines.
In another embodiment of the method, to test the memory cells within the region of intersection, initially the second address part of the column address is incremented, and, after the relevant row line has been fully tested, the second address part of the row address is incremented. To ascertain the group that needs to be tested next, the first address part of the column address is incremented. This means that testing is carried out locally along row lines within the region of intersection, with the row lines within the region of intersection being processed successively. The procedure then continues with the next group of column lines.
Accordingly, by changing the addressing sequence, another embodiment of the method provides that, to test the memory cells within the region of intersection, first the second address part of the column address is incremented, and, after the relevant row line has been fully tested, the second address part of the row address is incremented, with the first address part of the row address being incremented in order to ascertain the group which needs to be tested next. This means that addressing takes place locally within the region of intersection in the same sequence as in the previously described embodiment of the method, but the next group of row lines is addressed as the next group that needs to be tested.
In accordance with another mode of the invention, to test the memory cells within the region of intersection, initially the second address part of the row address is incremented, and, after the relevant column line has been fully tested, the second address part of the column address is incremented. To ascertain the group that needs to be tested next, the first address part of the column address is incremented.
In accordance with another mode of the invention, to test the memory cells within the region of intersection, initially the second address part of the row address is incremented. And, after the relevant column line has been fully tested, the second address part of the column address is incremented. To ascertain the group that needs to be tested next, the first address part of the row address is incremented.
The addressing unit of the memory according to the invention is configured such that the addresses of the memory cells can be generated in the sequence described. The addresses of the memory cells, which are each split into a first address part and a second address part, are generated by separate cooperating counters. In this context, the respective counters are driven in a suitable manner by the addressing unit. The respective address parts for the memory cells can go be tapped off at the outputs of the respective counters.
In accordance with another feature of the invention, the memory has a first counter for generating the first address part of the row address, a second counter for generating the second address part of the row address, a third counter for generating the first address part of the column address, and a fourth counter for generating the second address part of the column address. This configuration is used to produce the respective address parts of the column address and row address independently of one another under the control of the addressing unit.
In another embodiment of the integrated memory, the integrated memory has a first counter for generating the first address part of the row address and column address, and a second counter for generating the second address part of the row address and column address.
For the counters used, any form of a finite automaton may be used provided that the automaton runs through all possible states and hence through all subaddresses. These include, in particular, linear counters, Gray code counters or shift registers with feedback and specific forms of cellular automatons.
To carry out the various embodiments of the method that are described, the addressing unit can advantageously be operated in a respective one of a plurality of settable operating modes. These differ in terms of the addressing sequence of the memory cells that are to be tested.
Although the invention is illustrated and described herein as embodied in an integrated memory and method for checking the operation of memory cells in an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.